As CMOS device dimensions continue to shrink below 200nm, one of the major limiting factors in scaling size will become the drain and source junction depth. Using fluorine to create shallower p type junctions during ion implant is one way to decrease the junction depth. The effect of fluorine on the implant and subsequent anneal processes was studied. A low temperature annealing process was developed to decrease junction depths although sufficient dopant activation is being studied.
Kempisty, Jeremy J.
"The Effect of Fluorine on Low Temperature Boron Activation in Ultra Shallow Junctions,"
Journal of the Microelectronic Engineering Conference: Vol. 11:
1, Article 11.
Available at: https://repository.rit.edu/ritamec/vol11/iss1/11